Staff Silicon Design Engineer

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THE ROLE:

AMD's strategic focus is on developing one-of-a-kind solutions through its Strategic Silicon Solutions (S3) based on the extensive set of intellectual property (IP) amassed across AMD processors, graphics and multimedia. Providing to customers a level of flexibility and differentiation that goes beyond standard AMD products, our business unit takes AMD to a new level of customer-centric design by integrating these building blocks with customer-specific IP to create tailor-made solutions using a flexible System-on-a-Chip (SoC) design methodology.
THE PERSON:

As a Senior Member of the Technical Staff for the pre-silicon IP design team, you will work closely with the architecture, IP design verification, SOC design/verification, DFT, physical design and product engineers to achieve first pass silicon success. As an IP Design lead, you will guide a team of design engineers through technical challenges, ensure the team delivers to its commitments, and enables the program to be successful.

KEY RESPONSIBLITIES:

• Provide guidance on technical issues faced by the design team
• Planning team deliverables throughout the program
• Design of IP subsystems with integration of AMD and other 3rd party IP (ARM, DSPs, NOCs )
• Contribute to the specification and quality checks (lint, CDC, and power rule checks) of power-gated digital designs
• Work collaboratively with other members of the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

PREFERRED EXPERIENCE:

• Significant full-time experience in IP hardware design
• Experience in subsystem development with embedded processors and data fabric architectures
• Prior technical leadership experience, subject matter expert
• Prior team leadership experience (small/mid-sized team)
• Experience with 3rd party IP integration
• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
• Power saving techniques, including clock gating and UPF-based power gating
• Detailed understanding of ASIC design flows
• Verilog simulation and lint tools
• CDC/RDC concepts and tools
• Outstanding problem-solving and analytical skills
• Outstanding interaction skills while communicating both written and verbally
• Ability to work with multi-level functional teams across various geographies
• Highly organized, able to prioritize and balance multiple work streams while working to meet and exceed goals

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.